1. Technical Field of the Invention
This invention pertains to dynamic logic circuits. In particular, this invention is directed to testing dynamic logic circuits that include a half-latch, also known as a keeper device. A novel apparatus and method is described for testing whether keeper structures in dynamic logic are defective.
2. Background Art
A keeper device maintains a dynamic logic gate's precharge state and adds significant robustness to the circuit. In comparison to static logic circuits, dynamic logic circuits require a pre-charge pulse (RESET signal) that is followed by an evaluation phase wherein input signal data causes the gate to evaluate (the input signal data) by outputting a high or low output signal. In static logic, typically there are PFET pull-up devices and NFET pull-downs that are both connected to receive input signal data sent to the static logic gate.
A useful feature of a dynamic logic gate is the use of a half-latch and inverter (shown in FIG. 1) to maintain a precharge state of the gate. FIG. 1 illustrates an example generic logic gate having a RESET input 11, a half-latch 10, inverter 13, an output, and an evaluate function determined by the structure of logic tree 12. The logic tree may be connected to the primary node A at only one point or at several points, depending on the logic function to be performed. A logic gate such as in this example can be defective in many ways. The objective of testing is to identify those defective gates. One of the defect modes affects the keeper device 10 and makes it inoperative. For the gate shown in FIG. 1, the PFET keeper 10 can have an open source, an open drain, or the gate stuck at a "1". When such a defect exists the gate will typically function "properly" as a result of the inherent capacitance in the node A at the top of the logic tree 12. It will not have the robustness required to ensure proper operation at all conditions, however. Currently there is no good way to test dynamic logic gates and ensure that the keeper devices are indeed intact.
Dynamic logic has both a precharge and an evaluate time during its normal operation. During precharge, a gate is reset so that its output(s) and primary internal node(s) are precharged to a given state, e.g., a high state (binary "1"). Then when data (In1 . . . InX) arrives, the gate evaluates and, if appropriate (e.g. the logic tree couples the primary node to ground), the internal node discharges and the output transitions to the opposite state. Dynamic logic gates are frequently designed with an inverter on the output and a half latch to hold the primary internal node at its precharge state. This is comparable to a kind of memory function because the primary node is held in a high or low ("1" or "0") precharge state.
In the operational sequence for a dynamic gate with an NFET dominated logic tree, the reset signal, pulsed low, pulls the primary node high, which causes the output to go low (through the inverter). The output, coupled to the half-latch PFET, keeps the half-latch on and the primary node is pulled and maintained high. The PFET half-latch thus maintains the gate in its reset state until data arrives. Even if "reset" goes high, the half-latch maintains the primary node high in a noisy environment.